What is the strongest strength level in Verilog?

Which of these is NOT a type of circuit model in Verilog?

If A = 4'b1XXZ and B = 4'b1XXZ, then what will be the output for A === B and A == B?

What are the major trade-offs for Constraint-Driven Optimization?

Which of the following statement(s) is/are true about the 'always' block in Verilog?

wire out;

assign out= a&b; 

The above code snippet describes which type of assignment? 

What is the correct explanation of the Replication operation {3{2'b01}}?

What is the purpose of the $display system task in Verilog?

Given that $display is the main system task for displaying the values of variables or strings or expressions, the format specifier %d or %D displays the variable in _______________

There are two statements marked as Assertion (A) and Reason (R). Choose the correct option.