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Digital-electronics Questions Set 81:

Quiz Mode

A typical FPGA has a greater gate density than a CPLD.

True

False

Not given

Null

Solution:

For what input conditions is the output of an RTL NOR gate at logic 1?

logic 1

+5V

Floating

When all inputs are at logic 0

Solution:

A device that converts Binary Coded Decimal (BCD) to seven-segment display is called

Encoder

Decoder

Multiplexer

None of these

Solution:

The output Q_n+1 of a JK flip-flop is given by,

Q_n+1 = J Q̅_n + K̅ Q_n

Q_n+1 = J̅ Q_n + K̅ Q̅_n

Q_n+1 = J Q̅_n + K Q̅_n

Q_n+1 = J̅ Q_n + K Q̅_n

Solution:

An overflow occurs in the ________

Middle position

Signed Bit

Most Significant Digit (MSD) position

Least Significant Digit (LSD) position

Solution:

Which of the following boolean expressions can be used to realize a half adder in AOI (AND-OR-Invert) form?

A⨁B

Both of them can be used.

None of them can be used.

A'B + AB'

Solution:

In Programmable Logic Devices (PLDs), there are provisions to perform interconnections of the gates internally, because of

High reliability

High conductivity

The desired logic implementation

The desired output

Solution:

On a positive edge-triggered SR flip-flop, the outputs reflect the input condition when:

The clock pulse is low

The clock pulse is high

The clock pulse transitions from low to high

The clock pulse transitions from high to low

Solution:

A one-bit comparator compares two inputs a and b, and produces 3 outputs p, q and r. p is 1 if a=b, q is 1 if a>b and r is 1 if a

p = a̅b̅ + a̅b, q = a̅b̅, r = ab

p = a̅b + ab̅, q = ab, r = a̅b̅

p = a̅b̅ + ab, q = a̅b, r = ab̅

p = a̅b̅ + ab, q = ab̅, r = a̅b

Solution:

Henry was given a PROM, in seconds he recognized it as an ultraviolet erasable PROM, how did he?

There is a small window on the chip

They will have a small violet dot next to the #1 pin

Their part number always starts with a “U”, such as in U12

By reading the label

Digital-electronics Questions Set 81:

A typical FPGA has a greater gate density than a CPLD.

Solution:

For what input conditions is the output of an RTL NOR gate at logic 1?

Solution:

A device that converts Binary Coded Decimal (BCD) to seven-segment display is called

Solution:

The output Q_n+1 of a JK flip-flop is given by,

Solution:

An overflow occurs in the ________

Solution:

Which of the following boolean expressions can be used to realize a half adder in AOI (AND-OR-Invert) form?

Solution:

In Programmable Logic Devices (PLDs), there are provisions to perform interconnections of the gates internally, because of

Solution:

On a positive edge-triggered SR flip-flop, the outputs reflect the input condition when:

Solution:

A one-bit comparator compares two inputs a and b, and produces 3 outputs p, q and r. p is 1 if a=b, q is 1 if a>b and r is 1 if a

Solution:

Henry was given a PROM, in seconds he recognized it as an ultraviolet erasable PROM, how did he?

Solution:

Related Question Sets:

Related Topics:

Digital-electronics Questions Set 81:

A typical FPGA has a greater gate density than a CPLD.

Solution:

For what input conditions is the output of an RTL NOR gate at logic 1?

Solution:

A device that converts Binary Coded Decimal (BCD) to seven-segment display is called

Solution:

The output Qn+1 of a JK flip-flop is given by,

Solution:

An overflow occurs in the ________

Solution:

Which of the following boolean expressions can be used to realize a half adder in AOI (AND-OR-Invert) form?

Solution:

In Programmable Logic Devices (PLDs), there are provisions to perform interconnections of the gates internally, because of

Solution:

On a positive edge-triggered SR flip-flop, the outputs reflect the input condition when:

Solution:

A one-bit comparator compares two inputs a and b, and produces 3 outputs p, q and r. p is 1 if a=b, q is 1 if a>b and r is 1 if a

Solution:

Henry was given a PROM, in seconds he recognized it as an ultraviolet erasable PROM, how did he?

Solution:

Related Question Sets:

Related Topics:

The output Q_n+1 of a JK flip-flop is given by,