What is process scheduling?

Consider a machine in which all memory reference instructions have only one memory address. How many frames are needed for these instructions?

What is the definition of locality in computer science?

In general, the two types of interrupt request lines are:

A system is in a safe state if

What is the optimal page replacement algorithm?

Which of the following conditions are required for a deadlock to be possible?

One way to ensure that the circular wait condition never holds is to _____

Consider the following multi-threaded code segment (in a mix of C and pseudo-code), invoked by two processes P1 and P2, and each of the processes spawns two threads T1 and T2:

int x = 0; // global Lock L1; // global main () { create a thread to execute foo( ); // Thread T1 create a thread to execute foo( ); // Thread T2 wait for the two threads to finish execution; print(x);} foo() { int y = 0; Acquire L1; x = x + 1; y = y + 1; Release L1; print (y); }

Which of the following statement(s) is/are correct?

1. At least one of P1 and P2 will print the value of x as 4
2. Both P1 and P2 will print the value of x as 2
3. Both T1 and T2, in both the processes, will print the value of y as 1
4. At least one of the threads will print the value of y as 2

Consider a pipelined processor with 5 stages, Instruction Fetch(IF), Instruction Decode(ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. Assume that the ID stage merely decodes the instruction and the register read is performed in the EX stage. The EX stage takes one cycle for ADD instruction and the register read is performed in the EX stage, The EX stage takes one cycle for ADD instruction and two cycles for MUL instruction. Ignore pipeline register latencies. Consider the following sequence of 8 instructions:

ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL

Assume that every MUL instruction is data-dependent on the ADD instruction just before it and every ADD instruction (except the first ADD) is data-dependent on the MUL instruction just before it. The speedup defined as follows.

Speedup = (Execution time without operand forwarding) / (Execution time with operator forwarding)

The Speedup achieved in executing the given instruction sequence on the pipelined processor (rounded to 2 decimal places) is