Senior Principal RFIC Design Engineer

Overview

Senior Principal RFIC Design Engineer responsible for designing high-performance RF and analog integrated circuit blocks across architecture, simulation, optimization, layout verification, testing support, and correlation.

What you'll do

• Design high performance RF and analog circuit blocks at transistor, block, and module levels.
• Build circuit architecture and perform circuit design, simulation, and optimization.
• Supervise and verify layout work for RF/analog blocks and modules.
• Prepare test plans and support testing team activities.
• Conduct reliability and yield assessment and develop modeling.
• Run simulation-to-bench and bench-to-test correlation and perform bench evaluation at silicon and application levels.
• Document design work and results.

What you'll need

• Hands-on design and development experience in RF and analog integrated circuits.
• Experience in full CMOS circuit design and development in areas such as RF/analog blocks (e.g., baseband amplifiers, low noise RF amplifiers, mixers, up/down converters, drivers/receivers/CDR, equalizers, power amplifiers).
• Experience with 40nm and below CMOS technology.
• A track record of successful design releases and mass production.
• Thorough knowledge of industry-standard EDA tools (e.g., Cadence, Mentor, Siemens, Ansys).
• Experience with RF/high-performance analog block layout (e.g., LNA, mixer, ADC/DAC).
• Knowledge of high-performance analog layout considerations (e.g., matching, EM-IR, SOA and mitigation techniques).

Details

• Location: San Jose, CA or Irvine, CA.