Digital Electronics: Sequential & Systems
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About this course
Combinational logic has no memory: the output is a function of the present input and nothing else. Sequential logic is where state enters, and with it the whole set of problems that only exist once a circuit can remember — setup and hold windows, clock skew, metastability, lockout states, race conditions. This course covers that half of digital electronics as practice questions, from the first latch through state machines, memories, and data converters.
Who this is for
Students who have the combinational material and are moving on to the part of the syllabus that carries most of the exam weight, plus anyone revising sequential logic for a placement test or a hardware interview. If flip-flops, counters, and state machines are new to you, start with Digital Electronics first — this course assumes you can already read a Boolean expression and minimise it without stopping to derive the method.
How MCQ practice works on Abekus
Topics break into subtopics, subtopics into individual lessons. Each lesson pairs short explanation cards with questions written for that lesson specifically, and shows a worked explanation immediately after you answer. Sequential logic rewards this format unusually well, because most of its difficulty is a small number of mechanisms applied over and over — once you have answered fifteen setup-and-hold questions, the timing arithmetic stops being arithmetic and becomes recognition.
MCQ practice vs video courses
Watching a lecture on metastability leaves you able to describe it. Answering questions about it tells you whether you can predict when a single-bit synchroniser is insufficient, or compute a maximum clock frequency from a set of path delays under time pressure. That gap between describing and predicting is exactly what exams and interviews probe, and only retrieval practice closes it. Video is the better first pass on an unfamiliar mechanism; questions are the better second, third, and fourth.
Mistakes this subject punishes
Sequential logic has a well-defined set of traps, and nearly all of them are confusions between two things that look similar:
- Setup versus hold violations — and which one a slower clock actually fixes (hold, it does not)
- Latch versus flip-flop transparency, and where a level-sensitive element silently passes data through
- Moore versus Mealy output timing, and why Mealy outputs can glitch
- Asynchronous versus synchronous reset priority relative to the clock edge
- The all-zero lockup state in an LFSR, and the modulus of a Johnson versus a ring counter
- Assuming a two-flop synchroniser makes a multi-bit bus safe to cross clock domains
- Confusing access time with cycle time on DRAM, and forgetting refresh entirely
Each of these has questions built around it in the relevant topic.
Best way to learn sequential logic
Follow the curriculum order — it is deliberate. Storage elements come before timing, because setup and hold only mean something once you know what is capturing the data. Timing comes before counters and state machines, because their failure modes are timing failures. Memories and converters sit late because they assume the rest. The one topic worth extra passes is timing and metastability: it is the most transferable material in the subject, the most commonly examined, and the least forgiving of a half-formed mental model.