Jobs By Abekus

Digital-electronics Questions Set 13:

Quiz Mode

The number of distinct Boolean expression of 4 variable is

Solution:

The minimum number of flip-flops needed to make a mod-300 counter is

Solution:

What is another name for a stack data structure?

FIFO memory

Flash memory

LIFO memory

LILO memory

Solution:

What is the binary equivalent of (17E.F6)₁₆?

1110 1011 1.0011

1 0111 1110.1111 011

1111 011.10111

1111110.00001

Solution:

What are carry generate combinations?

If all the inputs are the same, then a carry is generated

If all the outputs are independent of the inputs

If all the inputs are dependent on the outputs

If all the outputs are dependent on the inputs

Solution:

TTL Family operates the Transistor in deep saturation mode, resulting in the limitation of Switching speed due to Storage delay time. To overcome this limitation, another Logic Family was developed. What Logic Family overcomes this limitation of TTL?

DCTL

Schottky TTL

ECL

Totem-pole TTL

Solution:

A 4-bit ripple counter and 4-bit synchronous counter are made using flip-flops with a propagation delay of 110 ns each. What is the worst-case delay in the ripple counter (R) and the synchronous counter (S)?

R=10 ns and S=40 ns

R=440 ns and S=110 ns

R=10 ns and S=30 ns

R=30 ns and S=10 ns

Solution:

The outputs of the full adder, Sum and Carry, are given to J and K respectively of a JK flip-flop. Initially, Q_n = 0 and Q'_n = 1. After a clock pulse, Q_n+1 = 1 and Q'_n+1 = 0. What should be the values of the inputs a, b, and c?

two or more inputs should be 1

only one input has to be 1, or all inputs should be 1

c should be zero, a, b can be 11 or 00

All inputs should be zero

Solution:

Consider a system where two flip-flops are connected to each other with combinational logic in between. The timing constraints are given below:

Flip-flop Setup time = 62 ps

Flip-flop Hold time = -10 ps

Worst-Case Clock-to-Q Delay = 90 ps

Best-Case Clock-to-Q Delay = 75 ps

Combinational Circuit Delay = 1 ns

Find the minimum clock period so that the system functions without contention and glitches.

2.054 ns

3.112 ns

1.152 ns

2.144 ns

Solution:

The parallel outputs of a counter circuit represent the ___________

Parallel data word

Clock frequency

Counter modulus

Clock count

Digital-electronics Questions Set 13:

The number of distinct Boolean expression of 4 variable is

Solution:

The minimum number of flip-flops needed to make a mod-300 counter is

Solution:

What is another name for a stack data structure?

Solution:

What is the binary equivalent of (17E.F6)₁₆?

Solution:

What are carry generate combinations?

Solution:

TTL Family operates the Transistor in deep saturation mode, resulting in the limitation of Switching speed due to Storage delay time. To overcome this limitation, another Logic Family was developed. What Logic Family overcomes this limitation of TTL?

Solution:

A 4-bit ripple counter and 4-bit synchronous counter are made using flip-flops with a propagation delay of 110 ns each. What is the worst-case delay in the ripple counter (R) and the synchronous counter (S)?

Solution:

The outputs of the full adder, Sum and Carry, are given to J and K respectively of a JK flip-flop. Initially, Q_n = 0 and Q'_n = 1. After a clock pulse, Q_n+1 = 1 and Q'_n+1 = 0. What should be the values of the inputs a, b, and c?

Solution:

Solution:

The parallel outputs of a counter circuit represent the ___________

Solution:

Related Question Sets:

Related Topics:

Digital-electronics Questions Set 13:

The number of distinct Boolean expression of 4 variable is

Solution:

The minimum number of flip-flops needed to make a mod-300 counter is

Solution:

What is another name for a stack data structure?

Solution:

What is the binary equivalent of (17E.F6)16?

Solution:

What are carry generate combinations?

Solution:

TTL Family operates the Transistor in deep saturation mode, resulting in the limitation of Switching speed due to Storage delay time. To overcome this limitation, another Logic Family was developed. What Logic Family overcomes this limitation of TTL?

Solution:

A 4-bit ripple counter and 4-bit synchronous counter are made using flip-flops with a propagation delay of 110 ns each. What is the worst-case delay in the ripple counter (R) and the synchronous counter (S)?

Solution:

The outputs of the full adder, Sum and Carry, are given to J and K respectively of a JK flip-flop. Initially, Qn = 0 and Q'n = 1. After a clock pulse, Qn+1 = 1 and Q'n+1 = 0. What should be the values of the inputs a, b, and c?

Solution:

Solution:

The parallel outputs of a counter circuit represent the ___________

Solution:

Related Question Sets:

Related Topics:

What is the binary equivalent of (17E.F6)₁₆?

The outputs of the full adder, Sum and Carry, are given to J and K respectively of a JK flip-flop. Initially, Q_n = 0 and Q'_n = 1. After a clock pulse, Q_n+1 = 1 and Q'_n+1 = 0. What should be the values of the inputs a, b, and c?