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Digital-electronics Questions Set 22:

Quiz Mode

The minimum number of NAND gates required to implement the expression A' B + A B' using only NAND gates is:

Solution:

The resolution of a 2-bit counting ADC is 1 V, and the input is 8.2 V. What is the digital output of the ADC?

1) 1110

2) 1010

3) 1011

4) 1001

Solution:

A 16 KB (= 16,384 bit) memory array is designed as a square with an aspect ratio of 1. What is the minimum number of address lines needed for the row decoder?

Solution:

If X=01110 and Y=11001 are two 5 bit binary numbers represented in 2's compliment form. The the sum of X and Y in 2's compliment using 7 bits is

0100111

0001000

0000111

1101001

Solution:

What happens when both inputs of an SR latch are low?

It remains in its previously set or reset state

It goes to its next set or reset state

The Q output goes high

The Q' output goes high

Solution:

For a n bit parallel adder how many Half adders and OR gates are required?

2n-1 Half Adders, n OR gates

2n Half Adders ,n-1 OR gates

2n+1 Half Adders, n OR gates

2n-1 Half Adders, n-1 OR gates

Solution:

JK flip-flops are used in a 3-bit module-8 ripple counter. What is the maximum clock frequency that can be used, if the propagation delay of each flip-flop is 50 ns?

20 MHz

6.66 MHz

10 MHz

3.33 MHz

Solution:

Which of the following statements about combinational and sequential circuits are correct?

A, B, and C are all correct

Only statement A is correct

Statements A and B are correct

Statements B and C are correct

Solution:

In a dual-slope integrating ADC, the first integration is carried out for 10 periods of the supply frequency of 50 Hz. If the reference voltage used is 2V, the total conversion time for an input of 1 V is

0.5s

0.4s

0.1s

Solution:

Which of the following statements about non-inverting buffers is not true?

They are used to drive circuits that need more drive current

They decrease the fan-out of the given logic

It is used as a delay line

None of the above

Digital-electronics Questions Set 22:

The minimum number of NAND gates required to implement the expression A' B + A B' using only NAND gates is:

Solution:

The resolution of a 2-bit counting ADC is 1 V, and the input is 8.2 V. What is the digital output of the ADC?

Solution:

A 16 KB (= 16,384 bit) memory array is designed as a square with an aspect ratio of 1. What is the minimum number of address lines needed for the row decoder?

Solution:

If X=01110 and Y=11001 are two 5 bit binary numbers represented in 2's compliment form. The the sum of X and Y in 2's compliment using 7 bits is

Solution:

What happens when both inputs of an SR latch are low?

Solution:

For a n bit parallel adder how many Half adders and OR gates are required?

Solution:

JK flip-flops are used in a 3-bit module-8 ripple counter. What is the maximum clock frequency that can be used, if the propagation delay of each flip-flop is 50 ns?

Solution:

Which of the following statements about combinational and sequential circuits are correct?

Solution:

In a dual-slope integrating ADC, the first integration is carried out for 10 periods of the supply frequency of 50 Hz. If the reference voltage used is 2V, the total conversion time for an input of 1 V is

Solution:

Which of the following statements about non-inverting buffers is not true?

Solution:

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