What are the possible values of a binary semaphore?

What is an uninterruptible unit called?

The overall I/O rate in RAID level 4 is ________

What is the minimum number of variables required to be shared between processes to solve the critical section problem?

How does scheduling affect the turn around time of a process?

Resource sharing helps ___________

Which of the following statements is/are TRUE with respect to deadlocks?

1. Circular wait is a necessary condition for the formation of deadlock.
2. In a system where each resource has more than one instance, a cycle in its wait-for graph indicates the presence of a deadlock.
3. If the current allocation of resources to processes leads the system to unsafe state, then deadlock will necessarily occur.
4. In the resource-allocation graph of a system, if every edge is an assignment edge, then the system is not in deadlock state.

The read access times and the hit ratios for different caches in a memory hierarchy are as given below:

The read access time of main memory in 90 nanoseconds. Assume that the caches use the referred-word-first read policy and the writeback policy. Assume that all the caches are direct mapped caches. Assume that the dirty bit is always 0 for all the blocks in the caches. In execution of a program, 60% od memory reads are for instruction fetch and 40% are for memory operand fetch. The average read access time in nanoseconds (up to 2 decimal places) is

Two processes X and Y need to access a critical section. Consider the following synchronization construct used by both the processes.

Here, varP and varQ are shared variables and both are initialized to false. Which one of the following statements is true?

Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.

OP Ri, Rj, Rk

where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.

I1 : ADD R1, R2, R3 I2 : MUL R7, R1, R3 I3 : SUB R4, R1, R5 I4 : ADD R3, R2, R4 I5 : MUL R7, R8, R9

Consider the following three statements:

S1: There is an anti-dependence between instructions I2 and I5. S2: There is an anti-dependence between instructions I2 and I4. S3: Within an instruction pipeline an anti-dependence always creates one or more stalls.

Which one of above statements is/are correct?