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Vhdl Questions Set 14:

Quiz Mode

What will be the value of x in the following code? SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;

-5

Solution:

The operator symbol '&' is used to concatenate two variables in VHDL

bitwise and

reduction and

concatenate

none of the above

Solution:

Which of the following is not defined by the entity?

Direction of any signal

Names of signal

Different ports

Behavior of the signals

Solution:

Which of the following is not an application of inertial delay?

Buffer delay

Simple delay in OR gate

Inverter delay

PC wireline delay

Solution:

Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?

Number of outputs

Number of inputs

Intermediate signals

No parameter

Solution:

Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?

x <= a + b; y <= a – b;

x <= a OR b; y <= a AND b;

x <= a + b; y <= a OR b;

x <= a OR b; y <= a + b;

Solution:

Refer to the VHDL code given below, which is the legal assignment statement?

`SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);`

y => x;

y := "0100";

y => "0100";

y <= (1 => '1', OTHERS => '0');

Solution:

What are the different styles used to describe architecture in VHDL?

It can be described using structural style

All of these

It can be described using dataflow style

It can be described using behavioral style

It can be described using mixed style

Solution:

What is the correct syntax for using the ASSERT statement?

ASSERT condition [REPORT string] [SEVERITY name];

Condition [REPORT string] [SEVERITY name] ASSERT;

Condition [SEVERITY name] [REPORT string] ASSERT;

ASSERT condition [SEVERITY name] [REPORT string];

Solution:

Which of the following is correct syntax for defining a configuration?

<pre class="ql-syntax" spellcheck="false">FOR instantation_label : component_name USE ENTITY library_name.entity_name[(architecture_name)]; </pre>

<pre class="ql-syntax" spellcheck="false">FOR instantation_label : component_name USE ENTITY entity_name[(architecture_name)]; </pre>

<pre class="ql-syntax" spellcheck="false">FOR component_name : instantiation_label USE ENTITY library_name.entity_name[(architecture_name)]; </pre>

<pre class="ql-syntax" spellcheck="false">FOR component_name : instantiation_label USE ENTITY entity_name[(architecture_name)]; </pre>

Vhdl Questions Set 14:

What will be the value of x in the following code? SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;

Solution:

The operator symbol '&' is used to concatenate two variables in VHDL

Solution:

Which of the following is not defined by the entity?

Solution:

Which of the following is not an application of inertial delay?

Solution:

Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?

Solution:

Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?

Solution:

Refer to the VHDL code given below, which is the legal assignment statement?

`SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);`

Solution:

What are the different styles used to describe architecture in VHDL?

Solution:

What is the correct syntax for using the ASSERT statement?

Solution:

Which of the following is correct syntax for defining a configuration?

Solution:

Related Question Sets:

Related Topics:

Vhdl Questions Set 14:

What will be the value of x in the following code? SIGNAL x : IN UNSIGNED (3 DOWNTO 0 ); x <= “1101”;

Solution:

The operator symbol '&' is used to concatenate two variables in VHDL

Solution:

Which of the following is not defined by the entity?

Solution:

Which of the following is not an application of inertial delay?

Solution:

Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?

Solution:

Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?

Solution:

Refer to the VHDL code given below, which is the legal assignment statement? SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);

Solution:

What are the different styles used to describe architecture in VHDL?

Solution:

What is the correct syntax for using the ASSERT statement?

Solution:

Which of the following is correct syntax for defining a configuration?

Solution:

Related Question Sets:

Related Topics:

Refer to the VHDL code given below, which is the legal assignment statement?

`SIGNAL x: STD_LOGIC; SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);`