Jobs By Abekus

Vhdl Questions Set 15:

Quiz Mode

Which of the following can have more than one driver?

OUT

INOUT

BUFFER

Solution:

Which of the following signal types can have more than one driver?

OUT

INOUT

BUFFER

Solution:

Antenna effect arises due to the

design defect

manufacturing process issues

radiation of signals

layout defect

Solution:

In VHDL, which data type can be used to declare memories?

2 Bit Vector

2 bit integer

2-dimensional Array

None of the above

Solution:

Where should a user declare a constant that needs to be accessible by the entire codebase?

Package

Entity

Architecture

Configuration

Solution:

Which of the following is the most basic form of behavioral modeling in VHDL?

IF statements

Assignment statements

Loop statements

WAIT statements

Solution:

What is the primary purpose of a signal in a circuit?

To set a default value

To declare a variable

To represent local information

To pass values between circuits

Solution:

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is for the positional mapping of the component?

LABEL : my_component PORT MAP (y, a);

LABEL : my_component PORT MAP (l => a, m => b, n => y);

LABEL : my_component PORT MAP (l, m, n);

LABEL : my_component PORT MAP(a, b, y >= a);

Solution:

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'?

`VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...`

y = 0100 and z = 0100

y = 0010 and z = 0100

y = 0100 and z = 1000

y = 0010 and z = 1000

Solution:

Which of the following VHDL code for a full adder is correct?

Library ieee; use ieee.std_logic_1164.all; entity full_adder is port(a,b,c:in bit; sum,carry:out bit); end full_adder; architecture data of full_adder is begin sum=> a xor b xor c; carry => ((a and b) or (b and c) or (a and c)); end data;

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is
begin
sum <= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is
begin
sum <= a xor b xor c;
carry >= ((a and b) or (b and c) or (a and c));
end data;

Vhdl Questions Set 15:

Which of the following can have more than one driver?

Solution:

Which of the following signal types can have more than one driver?

Solution:

Antenna effect arises due to the

Solution:

In VHDL, which data type can be used to declare memories?

Solution:

Where should a user declare a constant that needs to be accessible by the entire codebase?

Solution:

Which of the following is the most basic form of behavioral modeling in VHDL?

Solution:

What is the primary purpose of a signal in a circuit?

Solution:

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is for the positional mapping of the component?

Solution:

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'?

`VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...`

Solution:

Which of the following VHDL code for a full adder is correct?

Solution:

Related Question Sets:

Related Topics:

Vhdl Questions Set 15:

Which of the following can have more than one driver?

Solution:

Which of the following signal types can have more than one driver?

Solution:

Antenna effect arises due to the

Solution:

In VHDL, which data type can be used to declare memories?

Solution:

Where should a user declare a constant that needs to be accessible by the entire codebase?

Solution:

Which of the following is the most basic form of behavioral modeling in VHDL?

Solution:

What is the primary purpose of a signal in a circuit?

Solution:

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is for the positional mapping of the component?

Solution:

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'? VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...

Solution:

Which of the following VHDL code for a full adder is correct?

Solution:

Related Question Sets:

Related Topics:

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'?

`VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...`