150+ Vhdl Questions - Set 15 [With Solutions]

Which of the following can have more than one driver?

IN

OUT

INOUT

BUFFER

Which of the following signal types can have more than one driver?

IN

OUT

INOUT

BUFFER

Antenna effect arises due to the

design defect

manufacturing process issues

radiation of signals

layout defect

In VHDL, which data type can be used to declare memories?

2 Bit Vector

2 bit integer

2-dimensional Array

None of the above

Where should a user declare a constant that needs to be accessible by the entire codebase?

Package

Entity

Architecture

Configuration

Which of the following is the most basic form of behavioral modeling in VHDL?

IF statements

Assignment statements

Loop statements

WAIT statements

What is the primary purpose of a signal in a circuit?

To set a default value

To declare a variable

To represent local information

To pass values between circuits

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is for the positional mapping of the component?

LABEL : my_component PORT MAP (y, a);

LABEL : my_component PORT MAP (l => a, m => b, n => y);

LABEL : my_component PORT MAP (l, m, n);

LABEL : my_component PORT MAP(a, b, y >= a);

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'?

`VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...`

y = 0100 and z = 0100

y = 0010 and z = 0100

y = 0100 and z = 1000

y = 0010 and z = 1000

Which of the following VHDL code for a full adder is correct?

Library ieee; use ieee.std_logic_1164.all; entity full_adder is port(a,b,c:in bit; sum,carry:out bit); end full_adder; architecture data of full_adder is begin sum=> a xor b xor c; carry => ((a and b) or (b and c) or (a and c)); end data;

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is
begin
sum <= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is
begin
sum <= a xor b xor c;
carry >= ((a and b) or (b and c) or (a and c));
end data

Library ieee;
use ieee.std_logic_1164.all;

entity full_adder is port(a,b,c:in bit; sum,carry:out bit);
end full_adder;

architecture data of full_adder is
begin
sum <= a xor b xor c;
carry >= ((a and b) or (b and c) or (a and c));
end data;

Qn. Sets

Vhdl Questions Set 15:

Vhdl Questions

Which of the following can have more than one driver?

Reveal Answer

Reveal Answer

Which of the following signal types can have more than one driver?

Reveal Answer

Reveal Answer

Antenna effect arises due to the

Reveal Answer

Reveal Answer

In VHDL, which data type can be used to declare memories?

Reveal Answer

Reveal Answer

Where should a user declare a constant that needs to be accessible by the entire codebase?

Reveal Answer

Reveal Answer

Which of the following is the most basic form of behavioral modeling in VHDL?

Reveal Answer

Reveal Answer

What is the primary purpose of a signal in a circuit?

Reveal Answer

Reveal Answer

A component has 3 ports - two inputs (a and b) and one output (y). Which of the following statements is for the positional mapping of the component?

Reveal Answer

Reveal Answer

Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'? VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...

Reveal Answer

Reveal Answer

Which of the following VHDL code for a full adder is correct?

Reveal Answer

Reveal Answer

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Refer to the VHDL code given below, what should be the output of the variables 'y' and 'z'?

`VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010; VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000; VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000; ... y := x SRL 2; z := x SLL 2; ...`