ASIC Design Engineer, DMTS/SMTS/MTS

Overview

ASIC design engineer role at Micron Technology covering CAD enablement, physical design and signoff, DFT, and custom/analog layout for memory and SoC products.

What you'll do

• Own the development, deployment, and support of scalable CAD tools, automation frameworks, design flows, and methodologies for NAND, DRAM, HBM, SoC, mixed-signal, and other advanced semiconductor products.
• Develop, improve, and maintain infrastructure for circuit build capture, layout, simulation, characterization, implementation, physical verification, and signoff workflows.
• Create robust software and scripts using Python, Tcl, SKILL, Shell, Perl, C/C++, Java, Lisp, or related languages to automate engineering workflows, analytics, and quality checks.
• Evaluate and integrate advanced EDA technologies, AI-assisted engineering solutions, and emerging methodologies to improve productivity, scalability, and silicon quality.
• Demonstrate AI-assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies.
• Leverage AI tools to automate tools and workflows.
• Apply artificial intelligence in workflows to improve build efficiency.
• Lead implementation and signoff activities across physical design, static timing analysis, and design for test for complex digital, memory, SoC, or mixed-signal products.
• Drive floor planning, power planning, placement, clock tree synthesis, routing, optimization, timing closure, and physical verification to meet power, performance, area, reliability, and schedule targets.
• Own multi-mode, multi-corner timing signoff, including constraints, setup and hold analysis, timing exceptions, signal integrity, ECOs, and closure across implementation achievements.
• Develop and implement DFT strategies, including scan insertion, ATPG, MBIST, LBIST, compression, verification, and silicon bring-up support to achieve manufacturing test coverage goals.
• Analyze and resolve congestion, IR drop, electromigration, clocking, signal integrity, and implementation issues throughout the design cycle.
• Lead custom layout activities, including floor planning, device placement, routing, matching, parasitic-aware optimization, and layout quality reviews.
• Perform parasitic extraction and modeling, and support circuit simulation, design validation, reticle experiments, tape-out revisions, and post-layout correlation.
• Complete layout and circuit verification using industry-standard simulation, extraction, DRC, LVS, and reliability verification tools.
• Partner with architecture, RTL, circuit design, verification, methodology, process technology, modeling, standards, product engineering, probe, assembly, test, and marketing teams to ensure design readiness and manufacturability.
• Drive standardization, documentation, training, user support, best-practice adoption, and continuous methodology improvement across global engineering teams.
• Provide technical leadership, mentorship, and subject-matter expertise; influence tool, flow, and methodology roadmaps while solving complex multi-functional challenges.
• Support tape-out, first-pass silicon success, production ramp, and interpersonal learning through focused execution and effective collaboration.

What you'll need

• Bachelor's or Master's degree or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent proven experience.
• Strong knowledge of VLSI and CMOS fundamentals, semiconductor build methodologies, and tradeoffs involving power consumption, efficiency, size, dependability, and manufacturability.
• Hands-on experience with industry-standard EDA environments for implementation, timing, test, simulation, extraction, layout, verification, and signoff.
• Relevant tools may include Cadence Innovus and Virtuoso, Synopsys ICC2 and PrimeTime, Siemens Tessent, Cadence Tempus and Modus, or equivalent platforms.
• Proficiency in Unix/Linux environments and one or more engineering programming or scripting languages such as Python, Tcl, SKILL, Shell, Perl, C/C++, Java, or Lisp.
• Demonstrated ability to develop maintainable automation, debug complex design and flow issues, analyze engineering data, and drive designs to closure.