Senior Engineer II - Backend Implementation

Overview

Senior Engineer II on the Microchip AES Design team, responsible for static timing analysis (STA) and backend implementation for large SOCs, including timing constraints (SDC) generation and timing closure for blocks and top level.

What you'll do

• Perform STA timing closure for multi-million gate hierarchical complex designs.
• Lead and drive team members to complete implementation activities.
• Complete timing closure for blocks and top level in advanced nodes.
• Develop constraints/SDC and perform pre- and post-layout timing closure.
• Optimize design performance through timing closure and power optimization.
• Develop and maintain design constraints and timing models.
• Analyze and debug timing issues.
• Analyze physical timing challenges and provide guidance for placement and CTS.
• Use metric-driven techniques to help ensure first-pass working silicon.
• Communicate regularly with the implementation and project team to resolve issues and communicate status to Project Management.
• Take ownership of full chip/subsystem complex design and flow challenges for implementation of multiple large and complex blocks and subsystems from 16nm to 3nm and below technology nodes.

What you'll need

• B.E/B.Tech/M.Tech in Electronics.
• 7+ years of STA experience in a fast-paced environment.
• Expertise in implementation activities: static timing and crosstalk analysis and timing closure.
• Expertise with STA tools (PrimeTime or Tempus).
• Strong programming knowledge in Perl, TCL, and/or Shell and Python scripting.
• Strong understanding of timing closure and power optimization techniques.
• Good understanding of Verilog.
• Excellent oral and written communication skills to work with teams across the globe.

Nice to have

• Experience on UPF/CPF.

Details

• Location: Hyderabad, India.
• Travel: 0% to 25%, occasional travel needed.