ASIC Design Verification Engineer - 7+ yrs

Overview

ASIC Design Verification Engineer responsible for building and managing the ASIC verification (DV) environment and ensuring full verification coverage across the ASIC lifecycle.

What you'll do

• Architect block, cluster, and top-level DV environment infrastructure.
• Develop DV infrastructure from scratch and improve existing DV environments.
• Create test plans and develop tests for qualifying designs using constraint random and advised stimulus.
• Ensure complete verification coverage via code/functional coverage implementation and review.
• Qualify RTL using gate level simulations on the netlist.
• Collaborate to debug issues during post-silicon bring-up and support emulation-based testing.
• Lead and manage the ASIC bring-up process.

What you'll need

• 7+ years of ASIC design verification experience.
• Proficiency in ASIC verification using UVM/SystemVerilog.
• Experience verifying sophisticated blocks, clusters, and top-level ASICs.
• Hands-on experience building test benches from scratch.
• Hands-on experience with SystemVerilog constraints, structures, and classes.
• Bachelor’s degree or equivalent experience in EE/CE or related field.

Nice to have

• Scripting experience with Perl and/or Python.
• Experience with data path verification and performance tests.
• Familiarity with Synopsis Ethernet VIP.
• Experience with U controller testing integration.
• Experience with gate-level simulation.
• Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP).
• Formal verification (iev/vc formal) knowledge.