ASIC Design Verification Engineer, Technical Leader

Overview

ASIC design verification engineer/technical leader in Cisco’s Silicon One development organization, working onsite in San Jose, CA to verify ASICs across simulation, emulation, and bring-up.

What you'll do

• Maintain and enhance existing design verification (DV) environments.
• Build test benches including scoreboard, agents, sequencers, and monitors for new blocks.
• Write test plans and develop test cases for verification.
• Debug regression failures and drive issues to module verification closure.
• Ensure complete verification coverage via code and functional coverage implementation/review.
• Use AI tools to develop methods and processes to improve DV quality.

What you'll need

• Bachelor’s degree with 8+ years or Master’s degree with 6+ years of relevant experience.
• Prior experience with SystemVerilog and UVM methodology.
• Experience verifying complex blocks, cluster and/or top level for ASIC/SoC.
• Experience building test benches from scratch.
• Hands-on experience with SystemVerilog constraints, structures, and classes.
• Experience with functional coverage and constrained random DV environments.
• Scripting skills in Perl and/or Python.

Details

• Onsite work from the San Jose, CA office.
• Application window expected to close on 08/04/2026.