ASIC Design Verification Engineering Leader

Overview

Lead ASIC design verification for next-generation Cisco data center solutions, building DV infrastructure and ensuring high-quality verification across silicon environments.

What you'll do

• Architect and build design verification (DV) infrastructure across block, cluster, and top-level environments.
• Drive maximum functional coverage and elite quality for highly complex silicon.
• Collaborate with design, emulation, and software teams on cross-team verification needs.
• Debug critical firmware issues during development and verification cycles.
• Take charge during hands-on ASIC bring-up.
• Provide technical leadership to support seamless integration and optimal hardware platform performance.

What you'll need

• Have a Bachelor’s degree plus 12 years of related experience (or a Master’s plus 8 years, or a PhD plus 5 years).
• Have recent (last 2-3 years) experience with Verilog, SystemVerilog, and UVM.
• Have recent (last 2-3 years) scripting language experience (Perl or Python).
• Have experience with ASIC design and verification processes, debugging, methodology, and tools.
• Have experience verifying blocks/clusters or full chip level for ASIC.