DFT Engineer - Hardware

Overview

NVIDIA is hiring a DFT Engineer to own design-for-test work across the full chip flow, from RTL design through silicon bring-up.

What you'll do

• Deliver end-to-end DFT from RTL design to gate-level scan insertion, verification (including JTAG, boundary scan, security mechanisms and test clocking across various test modes and multiple ATPG configurations) and silicon bring-up.
• Verify and bring up silicon for Scan ATPG and other DFT features.
• Help develop and deploy DFT methodologies for next-generation products.
• Work with multi-functional teams to incorporate DFT features into the chip.

What you'll need

• BSEE or MSEE from reputed institutions, or equivalent experience, with 2+ years of experience.
• Well versed in static timing analysis, ECO, ASIC/logic design flow, HDL and digital logic design.
• Experience in RTL and gate-level verification and simulation.
• Familiarity with BIST architecture and JTAG/IEEE 1149.1/IEEE 1500.
• Strong DFT knowledge in Scan ATPG, compression techniques and memory test.
• Strong analytical and problem-solving skills with good scripting knowledge (Perl or Python).

Details

• Location: Bengaluru, India.
• Work mode: Hybrid.
• Occasional travel and some late-hours online meetings during critical milestones.