Digital Design Verification Engineer

Overview

Join the Design Verification team as a Digital Design Verification Engineer working on high-speed SerDes and PHY blocks for interfaces such as PCIe and Ethernet.

What you'll do

• Develop SystemVerilog/UVM verification environments.
• Maintain verification environments for SerDes and PHY blocks.
• Write testbenches, functional coverage models, and assertions.
• Run simulations and analyze failures.
• Debug RTL and testbench issues.
• Collaborate with design, architecture, and analog teams.

What you'll need

• BSc in Electrical Engineering, Computer Engineering, or equivalent.
• 0–5 years of digital design or verification experience.
• Working knowledge of SystemVerilog.
• Basic familiarity with UVM concepts.
• Knowledge of synchronous logic, FSMs, pipelining, and clock domain crossing.
• Strong analytical and debugging skills.
• Good spoken and written English communication skills.

Details

• Location: Iași, Romania.
• Remote role.
• Regular job type.
• Shift 1, Romania.