Principal Design Verification Engineer

Overview

Principal Design Verification Engineer to lead full-lifecycle verification for complex ASIC/SoC designs, focusing on robust verification methodology and functional coverage closure.

What you'll do

• Lead functional verification activities for advanced ASICs.
• Create and execute test plans and perform coverage analysis.
• Develop and run directed and constrained-random tests using SystemVerilog/UVM.
• Debug test failures and analyze coverage to close functional coverage gaps.
• Collaborate with software and system validation teams on emulation platform test plans.
• Troubleshoot and resolve design issues with RTL designers.
• Drive verification strategy and methodology for SoCs targeting server and networking applications.

What you'll need

• Bachelor’s degree in Electrical Engineering; Master’s preferred.
• 8+ years of experience in SoC verification, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM across the full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing/executing test sequences and generating stimuli.
• Familiarity with switching architectures including packet processing and forwarding engines.

Nice to have

• Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand.
• Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators.
• Knowledge of Ethernet/PCIe switching and central buffer architectures.
• Experience with emulation platforms and hardware-software co-verification.

Details

• Salary range: $185,000 to $230,000, depending on experience, level, and business need.