Research Engineer, Chip Design RL (Reinforcement Learning)

Overview

Research Engineer on the Code RL team for reinforcement learning that improves models’ ability to design silicon.

What you'll do

• Invent, design, and implement RL environments and evaluations for agentic RTL generation and design.
• Build RL workflows that include formal verification, physical design optimization, and related evaluations.
• Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• Conduct experiments and shape the team roadmap.
• Deliver work into research and production training runs.
• Collaborate with researchers and engineers across and outside Anthropic.

What you'll need

• Expertise in ASIC or FPGA design across RTL, design verification (UVM, formal methods, coverage-driven), and/or physical design (synthesis, place-and-route, timing closure).
• Experience with PPA optimization, DFT, ECOs.
• Fluency with industry EDA tools and processes.
• Experience with taping out chips and going from spec to silicon.
• Ability to balance research exploration with engineering implementation.
• Commitment to developing safe and beneficial systems.

Details

• Hybrid policy: expected to be in an office at least 25% of the time.