Senior ASIC Design Verification Engineer

Overview

Senior ASIC Design Verification Engineer responsible for building and running ASIC verification environments and performing end-to-end verification, coverage, and post-silicon bring-up analysis.

What you'll do

• Develop and maintain block, cluster, and top-level design verification environment infrastructure.
• Perform end-to-end verification of design blocks and top-level.
• Develop simulation models and test plans.
• Direct and random test execution with code or functional coverage.
• Run multi-chip/system simulation and support post-silicon bring-up and performance analysis.
• Ensure verification coverage via code and functional coverage implementation and review.
• Collaborate with designers, architects, software teams, and vendors.

What you'll need

• Bachelor’s degree in Electrical or Computer engineering with 7+ years of ASIC-related experience, or Master’s degree with 4+ years, or PhD with 1 year.
• Prior experience in SystemVerilog and UVM.
• Experience with ASIC design and verification processes, debugging, methodology, and tools.
• Experience verifying blocks/clusters/full chip level for ASIC.
• Ability to lead multiple tasks with clear written and verbal communication.