Senior Engineer-ASIC Design Verification

Overview

Senior ASIC Design Verification engineer responsible for IP, block and sub-system verification on the newest technology nodes, from test plan creation through to signoff.

What you'll do

• Be part of a highly skilled ASIC team working on the newest technology nodes.
• Be responsible for overall IP/Block and sub-system verification, from test plan creation and SystemVerilog/UVM testbench development to signoff.
• Ensure first-pass product through multi-dimensional verification coverage, including mixed-mode verification.
• Mentor and coach junior team members.
• Pair with similar domain specialists across other geographical locations on core technical initiatives.
• Utilize Micron-approved AI tools and AI-enabled workflows to improve engineering productivity.

What you'll need

• Expertise in IP/Block/Subsystem level verification and AMBA protocols (APB/AHB/AXI).
• Proven track record of building test plans, UVM environments and testbenches.
• Experience with RTL debugging, scoreboards, assertions, functional coverage coding and code coverage analysis.
• Sound knowledge of Verilog and SystemVerilog languages.
• Good written and verbal communication skills, with a strong commitment and ability to work in cross-functional and globally dispersed teams.
• 4+ years of experience.
• M.S./M.Tech or BS/BE in Electronics.

Details

• Location: Hyderabad, Phoenix Aquila, India.