Senior Engineer (Level 1)

Overview

Senior Engineer (Level 1) role focused on design verification of ASICs and SoCs, including server-class microprocessor-based SoCs and mixed-signal or SoC automotive ASICs.

What you'll do

• Troubleshoot errors at any stage of the process.
• Perform IP and SoC level verification using SV and/or UVM.
• Drive verification through assertions and coverage.
• Verify mixed-signal or SoC automotive ASICs.
• Apply Metric-driven Verification (MDV) and/or Formal Verification methodologies.
• Develop and track verification plans.
• Integrate VIP (Verification IP).
• Measure and analyze regression results.
• Define block-level and full-chip level test environments for server-class microprocessor-based SoC.
• Create test plans for unit-level and chip-level verification.
• Design and implement test benches and verification environments.
• Generate tests, debug failures, and evaluate design coverage.

Details

• Location: Hyderabad, India (Gowra Palladium, eInfochips).
• Employment type: Full time.