Senior Engineer (Level 2)

Overview

Senior Engineer (Level 2) role focused on SoC/IP/block-level functional verification using SystemVerilog and UVM.

What you'll do

• Develop test plans, testbench components, verification environments, interface agents and scoreboards in UVM.
• Debug RTL and testbench issues and test failures.
• Drive verification closure by closing coverage and bug reports.
• Develop and maintain scripts.
• Adapt to customer dynamic environment changes and run-time changes in schedule and design.

What you'll need

• 4 to 8 years of experience in SoC/IP/block-level functional verification using SystemVerilog/UVM.
• Strong knowledge of UVM, advanced UVM and SystemVerilog.
• Experience developing test plans, testbench components, verification environments, interface agents and scoreboards in UVM.
• Executed at least 1 to 2 SoC/IP verification projects.
• Knowledge of at least one industry standard protocol such as Ethernet, PCIe, MIPI, USB, AMBA or similar.
• Skills to debug RTL and testbench issues and test failures.
• Experience on verification closure by closing coverage and bug reports.
• Primary knowledge of script development and maintenance.
• Understanding of customer dynamic environment changes and adopting run-time changes in schedule and design.

Nice to have

• Understanding of the complete functional verification cycle.

Details

• Location: Hyderabad (Gowra Palladium, Kondapur), India.
• Employment type: Full time.