Senior / Lead Embedded Software Engineer - Zephyr RTOS

Overview

Lead Zephyr RTOS architecture and platform enablement for MIPS RISC-V based MCU and embedded compute products, combining hands-on low-level development with technical ownership, upstream engagement, mentoring and cross-functional delivery.

What you'll do

• Own the Zephyr enablement architecture and technical roadmap across MIPS RISC-V processors, SoCs, FPGA platforms and virtual development platforms.
• Lead porting and platform bring-up covering boot flow, exception and interrupt handling, timers, SMP where applicable, memory architecture, devicetree, Kconfig and build integration.
• Define scalable BSP, SoC, board and driver architecture aligned with Zephyr conventions and upstream-quality expectations.
• Design and review device drivers, middleware integration, samples, tests and production-quality SDK deliverables.
• Lead complex debugging across kernel, toolchain, architecture, hardware and driver boundaries using emulation, FPGA and silicon.
• Establish automated build and regression strategy using Zephyr testing infrastructure and CI/CD systems.
• Drive upstream contributions, technical discussions, reviews and maintenance strategy within the Zephyr ecosystem.
• Work closely with CPU architecture, SoC, FPGA, tools, validation, safety and customer teams; convert product requirements into executable software plans.
• Mentor engineers, raise engineering quality and provide technical direction without losing hands-on ownership.

What you'll need

• 8+ years of embedded software development experience, with substantial hands-on work in C and low-level platform software.
• Deep Zephyr RTOS expertise across kernel configuration, architecture or SoC ports, devicetree, Kconfig, west/CMake, board support, drivers and test infrastructure.
• Strong understanding of RTOS internals, concurrency, interrupt architecture, memory management, boot flows, multicore systems and real-time performance.
• Proven experience leading complex BSP, SDK, RTOS or silicon-enablement programs from architecture through release.
• Experience with bare-metal firmware, first-board or first-silicon bring-up, device drivers and hardware/software debugging.
• Strong debugging capability using GDB, OpenOCD, Segger J-Link, Lauterbach, trace tools and hardware logs.
• Experience with CI/CD, test automation, Python or shell scripting, code review, release quality and software configuration management.
• Ability to communicate architecture and execution trade-offs clearly to hardware, software, program and customer stakeholders.

Nice to have

• Zephyr maintainer-level expertise or meaningful upstream contribution history.
• RISC-V architecture expertise, including privilege modes, interrupts, timers, SMP, cache or memory-ordering considerations and toolchain integration.
• Experience with networking, Ethernet, TCP/IP, security, MCUboot, secure firmware update or device management.
• Experience enabling RTOS software on pre-silicon models, FPGA and production silicon.
• Exposure to functional safety or secure software development for automotive, industrial or infrastructure applications.

Details

• Location: Pune, Maharashtra, India.