Staff Design Verification Engineer – SoC and eFPGA

Overview

Staff Design Verification Engineer focused on end-to-end silicon verification for next-generation eFPGA technology and the SoCs that integrate it.

What you'll do

• Partner with architecture, RTL, firmware, and software teams to define verification strategies for new features.
• Develop verification plans for feature interactions, system-level behavior, and hardware/software use cases.
• Build and maintain directed and constrained-random verification environments and test suites.
• Create SystemVerilog assertions and functional coverage models.
• Debug simulation failures, determine root causes, and work with design and firmware engineers to resolve issues.
• Analyze functional/code coverage metrics to improve content and meet coverage goals.
• Support end-to-end eFPGA verification flows including RTL simulation, synthesis validation, and bitstream generation.

What you'll need

• Master's degree in EE/CE/CS or related field, or equivalent industry experience.
• Strong understanding of SoC architectures and bus protocols such as AXI and AHB.
• Experience debugging RTL and firmware using simulation and waveform analysis tools.
• Hands-on experience developing UVM-based verification environments.
• Proficiency in SystemVerilog, Verilog, C/C++, and Python.
• Experience developing automation solutions and working within distributed compute environments.
• Working knowledge of SystemC and Transaction-Level Modeling (TLM).

Details

• Travel: Yes, 10% of the time.
• Shift type: 1st Shift/Days.