Staff ENGINEER, HIG HBM-ARCHITECTURE

Overview

As an HBM Design Architect, you will define how next-generation HBM products are tested from wafer to system. The role focuses on quality, yield, and performance across complex multi-die architectures and involves hands-on silicon work with design, test, and manufacturing teams.

What you'll do

• Define and implement end-to-end DFT architectures for HBM base die and DRAM die.
• Develop DFT strategies for stacked-die, cube-level, and system-level test flows.
• Architect test access mechanisms supporting wafer probe through final test.
• Enable silicon observability for yield learning, debug, and failure analysis.
• Collaborate across design, verification, layout, test, and manufacturing teams.
• Leverage AI for design quality improvement and DFT.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong knowledge of scan, MBIST, JTAG, and boundary scan concepts.
• Experience with wafer probe and final test semiconductor flows.
• 5+ years of experience in DRAM or ASIC DFT design or verification.

Nice to have

• Experience with HBM, DRAM, or advanced memory products.
• Knowledge of TSV-based 3D integration and stacked-die test challenges.
• Hands-on experience with at-speed test or advanced DFT techniques.
• Exposure to DFT security features or custom customer test interfaces.
• Prior experience using AI to improve DFT coverage is higher desired.

Details

• Location: Bengaluru, Karnataka, India.