Verification Engineer

Overview

Intel is seeking a highly qualified ASIC design verification engineer to define and execute verification strategy for next-generation semiconductor products, while leading custom SystemVerilog/UVM development and mentoring junior engineers.

What you'll do

• Define project-specific verification strategy, implementing scalable and reusable verification plans, test benches and verification environments for blocks, subsystems and SoCs, ensuring required coverage levels and conformance to microarchitecture specifications.
• Lead verification execution by creating detailed test plans and driving technical reviews with design and architecture teams to validate these plans and proofs.
• Implement and run block/subsystem/cluster/SoC simulation models to verify the design, analyze power and performance, and identify bugs.
• Replicate, root-cause and debug issues in the pre-silicon environment, and implement corrective measures to resolve failing tests.
• Collaborate with SoC architects, micro architects, full chip architects, RTL developers, post-silicon and physical design teams to improve verification of complex architectural and microarchitectural features.
• Continuously improve existing functional verification infrastructure and methodologies.
• Learn from post-silicon validation quality, update the test plan for missing coverage, and proliferate improvements to future products.
• Lead and mentor junior engineers, fostering their growth and development.

What you'll need

• Bachelor's degree in electrical engineering, computer engineering, computer science, or other relevant STEM degree.
• 6+ years of experience in ASIC/FPGA design verification.
• Strong understanding of object-oriented programming (OOP) principles and their application in SystemVerilog UVM or other verification methodologies.
• Developing UVM and/or formal-based verification architectures and methodologies.
• Experience with industry-standard protocols: AMBA AXI/AXI-S/CHI and low-speed communication protocols (UART, SPI, I2C/I3C).
• Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
• Familiarity with coverage-driven verification, constrained-random testing and strong debugging skills.
• Experience with scripting languages.

Nice to have

• Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ years of experience.
• Skilled in various validation concepts and debug techniques relevant to the ASIC/FPGA domain.
• Collaborative, able to communicate well with counterparts and stakeholders; strong written and verbal communication skills.
• Strong analytical ability and problem-solving skills.
• Experience in defining testbench architecture and constrained random verification methodologies.
• Experience in processor-based verification using C/C++ with UVM-based verification environments.
• Define and execute validation of IPs and/or SoCs from spec to tape-in, including setting verification strategy, creating test benches and components, defining test plans, writing tests, debugging, coverage and analysis.
• Low power experience (e.g., UPF).
• Experience in AMBA, CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
• Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd-party VIPs.
• Experience with formal verification techniques and tools.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Shift: Shift 1 (India).
• Job type: Experienced Hire.