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Digital-electronics Questions Set 144:

Quiz Mode

How many unused states are present in a 5-bit Ring Counter?

Solution:

How many 2:1 multiplexers (muxes) are required to implement one 4:1 mux?

Solution:

What is the minimum number of NOR gates required to realize an XOR (exclusive OR) gate?

Solution:

Simplify the given boolean function (using boolean algebra laws)

f(x,y,z) = xx'z' + x'yz' + x'zz' + xyz' + yyz' + yzz'

xyz'

yz'

xyz

Solution:

Why are anti-fuses used in Programmable Logic Devices (PLDs)?

To protect from high voltage

To implement programs

As a switching device

To increase the memory

Solution:

What are the advantages of Gray code?

It is used in transmission of digital signals

It is used for labelling the axes of K-map

It is used in angle-measuring devices

Both a and b

Solution:

Which of the following Boolean functions will satisfy the property that the dual of the function is the complement of the function?

f(A, B, C) = Σm(0, 1, 2, 3)

f(A, B, C) = Σm(4, 5, 6, 7)

f(A, B, C) = Σm(0, 2, 4, 6)

f(A, B, C) = Σm(0, 1, 6, 7)

Solution:

The output of a 2:1 multiplexer is given by the expression Q = ~clkQ + clkD, where clk refers to the clock signal and D is the input. This multiplexer behaves as:

Negative D latch

Positive D latch

Positive edge D flip-flop

Negative edge D flip-flop

Solution:

What type of triggering is there in the given flip flop?

negative edge triggering

Both

None

positive edge triggering.

Solution:

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

74134

LPM

Synchronous

AHDL

Digital-electronics Questions Set 144:

How many unused states are present in a 5-bit Ring Counter?

Solution:

How many 2:1 multiplexers (muxes) are required to implement one 4:1 mux?

Solution:

What is the minimum number of NOR gates required to realize an XOR (exclusive OR) gate?

Solution:

Simplify the given boolean function (using boolean algebra laws)

f(x,y,z) = xx'z' + x'yz' + x'zz' + xyz' + yyz' + yzz'

Solution:

Why are anti-fuses used in Programmable Logic Devices (PLDs)?

Solution:

What are the advantages of Gray code?

Solution:

Which of the following Boolean functions will satisfy the property that the dual of the function is the complement of the function?

Solution:

The output of a 2:1 multiplexer is given by the expression Q = ~clkQ + clkD, where clk refers to the clock signal and D is the input. This multiplexer behaves as:

Solution:

What type of triggering is there in the given flip flop?

Solution:

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

Solution:

Related Question Sets:

Related Topics:

Digital-electronics Questions Set 144:

How many unused states are present in a 5-bit Ring Counter?

Solution:

How many 2:1 multiplexers (muxes) are required to implement one 4:1 mux?

Solution:

What is the minimum number of NOR gates required to realize an XOR (exclusive OR) gate?

Solution:

Simplify the given boolean function (using boolean algebra laws) f(x,y,z) = xx'z' + x'yz' + x'zz' + xyz' + yyz' + yzz'

Solution:

Why are anti-fuses used in Programmable Logic Devices (PLDs)?

Solution:

What are the advantages of Gray code?

Solution:

Which of the following Boolean functions will satisfy the property that the dual of the function is the complement of the function?

Solution:

The output of a 2:1 multiplexer is given by the expression Q = ~clk*Q + clk*D, where clk refers to the clock signal and D is the input. This multiplexer behaves as:

Solution:

What type of triggering is there in the given flip flop?

Solution:

The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

Solution:

Related Question Sets:

Related Topics:

Simplify the given boolean function (using boolean algebra laws)

f(x,y,z) = xx'z' + x'yz' + x'zz' + xyz' + yyz' + yzz'

The output of a 2:1 multiplexer is given by the expression Q = ~clkQ + clkD, where clk refers to the clock signal and D is the input. This multiplexer behaves as: