Digital-electronics Questions Set 147:
How many flip-flops are needed to design a mod-13 counter?
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What is the output frequency of 4 flip-flops when the input clock frequency is 256 kHz?
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Which of the following components is NOT used to design a Universal Shift Register?
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Which combinational circuit is used to reduce the number of select lines in a memory system?
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Which of the following sets of Boolean logic gates is logically complete?
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Which type of counter is designed such that only the first flip-flop in the circuit is given an external clock signal?
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Three cascaded decade counters will divide the input frequency by ____________
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Internal propagation delay of asynchronous counter is removed by _________
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What are the three output conditions of a three-state buffer?
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Registers capable of shifting in one direction are called____
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