Each entry in a translation lookaside buffer (TLB) consists of a ____________

The only state transition that is initiated by the user process itself is __________

The TestAndSet instruction is executed ____________

If one or more devices use a common set of wires to communicate with a computer system, the connection is called a ______

The hybrid algorithm that combines Earliest Deadline First (EDF) with the SCAN algorithm is known as ___________

Under multiprogramming, turnaround time for short jobs is usually lengthened and that for long jobs is slightly shortened.

A graphics card has an onboard memory of 1 MB. Which of the following display modes can the card not support?

A cache memory unit with capacity of N words and block size of B words is to be designed. If it is designed as direct mapped cache, the length of the TAG field is 10 bits. If the cache unit is now designed as a 16-way set-associative cache, the length of the TAG field is ______ bits

The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is

Consider the following statements about process state transitions for a system using preemptive scheduling.

• I. A running process can move to ready state.
• II. A ready process can move to running state.
• III. A blocked process can move to running state.
• IV. A blocked process can move to ready state.

Which of the above statements are TRUE ?