Signals of a given type are:

In which scheduling algorithm are processes classified into different groups?

A __________ is a device where the driver communicates the entire blocks of data.

The CPU fetches instructions from memory according to the value in the __________ register.

Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies v₁, v₂, and v₃ such that v₁ = 3v₂/4 = 2v₃. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline registers

Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is 1 GHz, then the clock frequency of P2 (in GHz) is _________

The following are some events that occur after a device controller issues an interrupt while process L is under execution. (P) The processor pushes the process status of L onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of L from the control stack. (T) The processor loads the new PC value based on the interrupt. Which of the following is the correct order in the which the events above occur?

Each of a set of n processes executes the following code using two semaphores a and b initialized to 1 and 0, respectively. Assume that count is a shared variable initialized to 0 and not used in CODE SECTION P.

CODE SECTION P wait(a); count=count+1; if (count==n) signal (b); signal (a): wait (b) ; signal (b); CODE SECTION Q

What does the code achieve ?

Consider the following snapshot of a system running n concurrent processes. Process i is holding X_i instances of a resource R, 1 ≤ i ≤ n. Assume that all instances of R are currently in use. Further, for all i, process i can place a request for at most Y_i additional instances of R while holding the X_t instances it already has. Of the n processes, there are exactly two processes p and q such that Y_p = Y_q = 0. Which one of the following conditions guarantees that no other process apart from p and q can complete execution?

Consider the sequence of machine instructions given below:

MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4

In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the Result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is ___________