AI System Performance Architect

Overview

Own the end-to-end understanding of AI training and inference systems, using analytical modelling and multi-GPU simulation to translate SLA and deployment targets into architectural guidance for Intel's future AI platforms.

What you'll do

• Own end-to-end understanding of the AI training/inference system and build analytical models and multi-GPU simulation, including MPI/collective communication (allgather, allreduce, all-to-all) and interconnect contention, to project performance, expose architectural bottlenecks, and recommend optimal Intel system configurations.
• Model inferencing strategies (static batching, continuous batching, disaggregated serving, and chunked prefill) across frameworks such as vLLM and SGLang, covering agentic inferencing, prefix caching, and multi-turn flows.
• Cover data, pipeline, tensor, and expert parallelism and their communication patterns.
• Drive studies against SLA targets: batch size, TTFT, TPOT, ISL/OSL, and TPS.
• Analyse regression run traces and find patterns in utilization counters across SLA operating points to identify architectural bottlenecks.
• Perform what-if analysis by sweeping core count, memory/cache capacity and bandwidth, fabric bandwidth, GPU interconnect, and deployment options; deliver optimization and optimal architecture recommendations.
• Scout whitepapers, blogs, and conferences; keep self and team updated on AI innovations applicable to Intel's end-to-end system.

What you'll need

• Bachelor's, master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Bachelor's with 8+ years, master's with 6+ years, or PhD with 3+ years of experience in system performance modelling, AI workload analysis, or hardware architecture.
• Strong proficiency in Python, with the ability to build modular, maintainable analytical models and simulation frameworks.
• Solid understanding of LLM inference and training mechanics: prefill vs. decode, KV cache, batching policies, and quantization.
• Working knowledge of distributed parallelism strategies and their communication patterns.
• Familiarity with multi-GPU interconnect architectures (NVLink, PCIe, CXL, or equivalent).
• Understanding of SoC and platform fundamentals: core count scaling, cache/memory capacity and bandwidth, and fabric behavior.

Nice to have

• Experience building discrete-event simulators for multi-node or multi-accelerator systems.
• Familiarity with performance profiling tools (e.g., Intel VTune, NVIDIA Nsight, or similar).
• Prior experience in a semiconductor or hardware company working on AI accelerator or platform products.

Details

• Location: India, Bangalore.
• Work model: hybrid, splitting time between on-site at the assigned Intel site and off-site.
• Experienced hire; Shift 1 (India).