ASIC Design Verification Engineer || Verilog, UVM, Testbench | Emulation || Exp 7+ years

Overview

Design Verification Engineer specializing in simulation and emulation, developing and executing verification strategies for complex ASIC hardware designs in Cisco's Silicon One group.

What you'll do

• Develop and implement verification plans and test benches using emulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

What you'll need

• Bachelor's + 7 years of related experience, or Master's + 4 years of related experience, or PhD + 1 year of related experience.
• Strong experience in design verification methodologies using UVM or OVM.
• Relevant experience in design verification with a strong emphasis on test methodologies.
• Exposure to emulation tools such as Cadence Palladium, Synopsys Zebu, etc.
• Experience with networking protocols such as Ethernet, AXI, AMBA, PCIe, etc.

Details

• Location: Bangalore, India.