ASIC Design Engineer | Simulation & Emulation , Test methodologies | 7 to 11 Years | Bangalore

Overview

Design Verification Engineer specializing in Simulation and Emulation for Cisco's Silicon One group, focused on developing and executing verification strategies for complex ASIC hardware designs, with primary emphasis on emulation platforms.

What you'll do

• Develop and implement verification plans and test benches using emulation tools and methodologies.
• Collaborate with design and validation teams to identify verification requirements and coverage goals.
• Utilize emulation platforms to run large-scale verification tests and debug design issues.
• Analyse verification results, identify bugs, and work closely with design engineers to resolve issues.
• Maintain and enhance verification infrastructure and automation frameworks.
• Document verification processes, test cases, and results to ensure traceability and reproducibility.
• Stay current with emerging verification technologies and best practices, particularly in emulation.
• Mentor junior engineers and contribute to team knowledge sharing.

What you'll need

• Bachelor's degree plus 7 years of related experience, or Master's degree plus 4 years of related experience, or PhD plus 1 year of related experience.
• Strong experience in design verification methodologies using UVM or OVM.
• Relevant experience in design verification with a strong emphasis on test methodologies.
• Exposure to emulation tools such as Cadence Palladium, Synopsys Zebu, etc.
• Experience in networking (Ethernet, AXI, AMBA, PCIe, etc.).
• Strong communication skills and ability to work as a team.

Nice to have

• Post-silicon functional validation or debugging experience.

Details

• Location: Bangalore, India.