IP Verification Lead Engineer, Sr

Overview

Senior IP Verification Lead Engineer role in hardware engineering, focused on IP-level verification using SystemVerilog and UVM.

What you'll do

• Develop testbenches from scratch and work across all testbench environment concepts.
• Debug design issues using the VCS tool.

What you'll need

• 6+ years of experience in IP-level verification.
• Good understanding of SystemVerilog and UVM concepts.
• Hands-on experience developing testbenches from scratch.
• Good understanding of digital and Verilog concepts.
• Good understanding of basic bus protocols such as AHB, AXI and APB.
• Good understanding of functional and code coverage.
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of hardware engineering or related work experience, OR Master's degree in a related field and 2+ years of hardware engineering or related work experience, OR PhD in a related field and 1+ year of hardware engineering or related work experience.

Nice to have

• Experience with security-related IP such as cryptography, PRNG and RSA algorithms.
• Understanding of the SiFive RISC processor.
• Formal verification tool knowledge, either VCF or JasperGold.

Details

• Location: Bangalore, India.