Senior Engineer II - Verification

Overview

Lead block-level verification activities for hardware designs, including planning, environment development, simulation, coverage analysis, and defect resolution.

What you'll do

• Develop verification test plans from design specifications.
• Build test environments using SystemVerilog and UVM.
• Integrate with RTL and perform basic design simulation bring-up.
• Create test cases and launch regression runs.
• Generate and analyze code and functional coverage.
• Work with design team members to identify and resolve design problems.

What you'll need

• More than 10 years of work experience.
• Bachelor’s or master’s degree in Electrical or Electronic Engineering or an equivalent qualification.
• Expertise in AHB, AXI, PCIe, USB, and Ethernet.
• Proficiency in Verilog and SystemVerilog.
• Experience with OVM or UVM methodologies.
• Experience with at least one of QuestaSim, VCS, NCSim, or NCVerilog.
• Experience developing testbench components at block and SoC levels.

Nice to have

• Experience with functional coverage, code coverage, and assertions including OVA, SVA, or PSL.

Details

• Location: Chennai, India.
• Travel: 0%–25%.