Technical Staff Engineer - Verification

Overview

Technical Staff Engineer responsible for verification of Ethernet MAC, PCS, and PHY for next-generation FPGA products. The role covers verification strategy, simulation-based functional verification, RTL debugging, and technical mentoring.

What you'll do

• Define verification specifications and comprehensive verification plans.
• Execute simulation-based functional verification using SystemVerilog and UVM.
• Debug RTL against design intent.
• Develop constrained-random and directed simulation test cases.
• Build UVM testbenches and functional coverage models.
• Execute regressions, analyze coverage gaps, and drive verification closure.
• Mentor engineers and share verification best practices.

What you'll need

• 12+ years of functional verification experience.
• Hands-on verification experience with Ethernet 40G/100G, 1588 PTP, and JESD204.
• Strong knowledge of Ethernet and AMBA AXI/AHB protocols.
• Experience with OVM/UVM, coverage-driven, and assertion-based verification.
• Strong scripting skills in Python, Shell, Perl, and TCL.
• Proficiency in SystemVerilog, Verilog, and VHDL.
• Bachelor’s or Master’s degree in Electrical Engineering or a related field.

Nice to have

• Knowledge of C-based test case development.

Details

• Location: Hyderabad, India.
• Travel: 0%–25%.