Technical Staff Engineer - Verification

Overview

Provide technical leadership for verification of next-generation Ethernet Switch and PCIe Switch SoCs integrating Ethernet, PCIe, ARM/MIPS CPU subsystems, and AMBA-based interconnect fabrics. Drive verification strategy and execution across IP, subsystem, and full-SoC levels using SystemVerilog UVM.

What you'll do

• Provide technical leadership for verification of complex Ethernet and PCIe Switch SoCs, including datapath, control-plane, management, and CPU subsystems.
• Define and drive verification architecture, methodologies, and best practices across projects and teams.
• Lead verification of ARM/MIPS CPU subsystems and AMBA-based interconnect fabrics including AXI, AXI-Lite, AHB, and APB.
• Architect scalable and reusable SystemVerilog UVM environments, agents, scoreboards, protocol checkers, and coverage frameworks.
• Drive verification planning and execution for PCIe link training and LTSSM, enumeration and configuration space, error handling and recovery, NTB, and hot-plug support.
• Verify AMBA protocol corner-case and error scenarios.
• Validate CPU subsystem boot and reset sequences, register access and RAL integration, DMA and memory interactions, interrupts, and timers.
• Develop constrained-random, directed, and scenario-based verification strategies for realistic traffic and system workloads.
• Drive functional, code, assertion, and cross-coverage closure with metrics-driven methodologies.
• Debug system-level issues spanning RTL, firmware interactions, AMBA fabrics, protocol layers, and UVM infrastructure.
• Leverage AI-assisted tools for regression triage, debug automation, coverage analytics, and intelligent test optimization.
• Collaborate with architecture, RTL, firmware, validation, emulation, and physical design teams.
• Mentor and technically guide verification engineers across multiple experience levels.
• Drive continuous improvement in regression infrastructure, reusability and scalability, and simulation and debug productivity.
• Contribute to verification roadmap planning and methodology standardization across programs.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• Typically 12+ years of ASIC/SoC verification experience with increasing technical leadership responsibilities.
• Expert-level proficiency in SystemVerilog and UVM, including advanced UVM architecture, reusable verification components, scoreboards and predictors, functional coverage modeling, sequence layering and virtual sequences, and UVM RAL methodology.
• Strong expertise in verifying AMBA-based interconnect fabrics: AXI, AXI-Lite, AHB, and APB.
• Proven experience verifying Ethernet and/or PCIe-based SoCs.
• Strong understanding of ARM and/or MIPS CPU architectures and subsystem integration.
• Deep understanding of SoC architecture and integration, memory hierarchies and DMA, interrupt and coherency mechanisms, and high-performance interconnect behavior.
• Extensive experience with industry-standard simulators and debug tools: VCS, Questa, and Xcelium.
• Strong scripting and automation expertise using Python, Perl, Tcl, or equivalent.
• Excellent analytical, debugging, communication, and technical leadership skills.

Nice to have

• Experience with SoC-level verification closure and multi-IP subsystem integration.
• Experience integrating firmware/software-driven verification flows.
• Exposure to AI/ML-based verification tools for intelligent debug, coverage optimization, automated failure classification, and test generation.
• Experience building or driving metrics-driven verification environments.
• Prior experience mentoring teams or leading technical initiatives across projects.

Details

• Location: Hyderabad, India.
• Travel time: 0%–25%.