Principal Engineer Verification

Overview

Lead integrated-circuit simulation, verification and validation, with ownership of verification quality, metrics and customer-facing technical communication.

What you'll do

• Perform and supervise simulation, verification and validation of integrated circuits.
• Develop SystemVerilog and UVM testbenches for functional and power-aware RTL.
• Build UVM agents, scoreboards, environments, assertions and functional coverage.
• Create test plans, UVM test sequences, layered sequences and virtual sequencers.
• Drive closure of verification metrics and resolve functional, power-aware and gate-level simulation gaps.
• Set up regressions and debug RTL and gate-level netlists.
• Support post-silicon bring-up, validation, compliance testing and customer design reviews.

What you'll need

• Bachelor's degree in electrical engineering or equivalent.
• 12+ years of experience.
• Proven expertise in UVM and/or SystemVerilog-based verification.
• Strong understanding and experience with ASIC verification methodologies.
• Experience with Jenkins, Git and Jira or comparable source control, bug management and release management tools.
• Strong written and verbal communication skills.
• Ability to work independently.

Details

• Location: Hyderabad, India.