PMTS, Design Verification Lead

Overview

Seeking an experienced Design Verification Lead to lead verification strategy, planning, execution, and signoff for next-generation RISC-V based Processor IP products.

What you'll do

• Own verification strategy and verification signoff for processor IP products and subsystems.
• Lead verification planning, methodology definition, execution, and closure activities.
• Define coverage goals, quality metrics, signoff criteria, and verification milestones.
• Architect scalable verification environments using SystemVerilog, UVM, assertions, and constrained-random methodologies.
• Lead processor verification across CPU cores, DSP extensions, vector processing units, MMUs, caches, interrupts, debug infrastructure, security features, and system interfaces.
• Drive bug triage, root-cause analysis, and closure activities; ensure deliverables meet quality and schedule objectives.

What you'll need

• Typically 12+ years of relevant industry experience in ASIC/SoC/processor verification.
• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Expert knowledge of SystemVerilog, UVM, Assertions (SVA), functional coverage, and constrained-random verification.
• Strong understanding of processor architecture and microarchitecture concepts.
• Experience with simulation, emulation, and regression infrastructures, coverage-driven verification, and verification signoff methodologies.
• Proven track record leading verification teams for complex CPU, MCU, DSP, or processor IP products.
• Excellent project leadership and communication skills.

Details

• Role involves leading a team of verification engineers across multiple projects.