Design Verification Engineer

Overview

Design Verification Engineer responsible for modeling and verification of complex digital and mixed-signal (MXS) IP blocks used in ASIC developments.

What you'll do

• Define verification plans and environment architecture.
• Develop test cases and test bench components.
• Perform coverage analysis and drive closure.
• Debug simulation failures at RTL and gate level.
• Develop functional models for block, system, and ASIC verification.
• Collaborate with design teams and EDA vendors on modeling and verification tasks.

What you'll need

• 12+ years of verification experience with complex digital and MXS circuits.
• Experience verifying designs at block and system levels.
• Experience using SystemVerilog and UVM.
• Experience building verification components such as UVM agents, checkers, and behavioral models.
• Experience creating random & directed test cases to achieve coverage goals and use SystemVerilog Assertions.
• Knowledge of RTL, gate-level netlists, and SDF for verification.

Details

• Works with emulation and FPGA prototyping platforms (may involve leading adoption of advanced verification methodologies/flows).
• Must have legal authorization to work in the US.