Design Verification Engineer, Coherent Interconnect

Overview

Design verification engineer for System IP, focused on coherent interconnects and caches.

What you'll do

• Execute verification strategy for coherent interconnect and cache System IP.
• Architect, develop, and maintain reusable verification environments and testbenches.
• Build verification components including stimulus, assertions, checkers, covergroups, and SystemVerilog constraints.
• Develop verification methodologies and improve verification flows and productivity.
• Verify key features using test plans, code and spec reviews, debugging regressions, and coverage analysis.
• Collaborate with design and SoC teams to analyze failures, resolve spec issues, and support bring-up.

What you'll need

• 10+ years of experience with a Bachelor’s degree, or 8+ years with a Master’s degree, or 6+ years with a Ph.D.
• 8+ years of professional experience in a design verification role building testbenches from scratch.
• Strong background in design verification of coherent interconnects.
• Proficiency in ARM protocols: CHI, AXI, ACElite, and APB.
• Coding skills in SystemVerilog and UVM.
• Experience with Git version control and Unix/Perl scripting.