Sr. Staff/Staff Design Verification Engineer

Overview

Sr. Staff/Staff Design Verification Engineer responsible for developing and executing verification strategies to ensure a high-quality design that works on first silicon.

What you'll do

• Work with architects, designers, post-silicon and software engineers to validate designs.
• Develop verification strategies, detailed tests, and coverage plans from micro-architecture.
• Create verification methodologies and reusable environments with stimulus, checkers, assertions, and coverage.
• Implement tests, manage regressions, collect coverage, and debug test failures.
• Collaborate with cross-functional teams across architecture, RTL, physical design, firmware, and validation.
• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
• Improve verification infrastructure and flows to increase efficiency and quality.

What you'll need

• 10+ years of Design Verification experience.
• Deep knowledge of SystemVerilog testbench, DPI, and UVM.
• Excellent programming skills and knowledge of software engineering practices, including object-oriented design.
• Experience developing scalable and portable testbenches and components.
• Experience with verification methodologies and tools including simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations.
• Scripting proficiency in Python or Perl.

Details

• Location: Sunnyvale, CA.
• Base salary range: $250,000 to $300,000 annually.