Staff Design Verification Engineer

Overview

Staff Design Verification Engineer responsible for building and executing design verification strategies to ensure high-quality silicon that works first pass.

What you'll do

• Work with architects, designers, post-silicon, and software engineers to deliver first-silicon success.
• Develop verification strategies, detailed tests, and micro-architecture-based coverage plans.
• Create verification methodologies and reusable environments using stimulus, checkers, assertions, and coverage components.
• Implement tests, manage regressions, collect coverage, and debug test failures.
• Collaborate with cross-functional teams across architecture, RTL design, physical design, firmware, and validation.
• Analyze and debug issues across simulation, emulation, and silicon bring-up phases.
• Improve verification infrastructure and flows and contribute to verification methodology best practices.

What you'll need

• 10+ years of design verification experience.
• Deep knowledge of SystemVerilog testbench, DPI, and UVM.
• Excellent programming skills and knowledge of object-oriented design and software engineering practices.
• Experience developing scalable and portable testbenches and components.
• Experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations.
• Proficiency in scripting languages such as Python or Perl.
• Good interpersonal skills, extremely self-motivated attitude, and strong problem-solving ability.

Details

• Location: Sunnyvale, CA.