Manager / Senior Manager – Design Verification

Overview

Manager / Senior Manager – Design Verification to lead IP and SoC verification across multiple projects.

What you'll do

• Lead and develop a Design Verification team for IP and SoC verification across multiple projects.
• Drive verification planning, execution, functional coverage closure, regression management, sign-off, and on-time delivery.
• Provide technical leadership in SystemVerilog, UVM, assertions, constrained-random verification, coverage-driven verification, and debug methodologies.
• Manage priorities, technical risks, resource allocation, and dependencies across multiple programs.
• Collaborate with Design, Architecture, Firmware, Validation, and Program Management teams across global sites.
• Improve verification methodologies and automation, including reusable verification infrastructure.

What you'll need

• 10–15 years of experience in Design Verification.
• Strong expertise in IP, subsystem, and SoC verification.
• Proven experience leading and developing Design Verification teams in a multi-site environment.
• Hands-on expertise in SystemVerilog, UVM, assertions, constrained-random verification, functional coverage, and regression management.
• Experience delivering complex verification projects from planning through sign-off.
• Strong understanding of verification planning, testbench architecture, coverage closure, debug methodologies, and verification metrics.
• B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Computer Engineering, VLSI, or a related field.

Details

• Role is based in Hyderabad.