SMTS - CPU Design Verification Engineer

Overview

Design verification engineer on the CPU verification team at MIPS, a GlobalFoundries company, focused on CPU core functionality, coherency and cache subsystems.

What you'll do

• Perform functional verification of CPU cores and related subsystems (MMU, Cache, Safety, Debug etc.).
• Understand and interpret microarchitectural specifications to develop effective verification strategies.
• Develop and execute verification plans, including testbench creation and test case development.
• Write directed and constrained random test cases in SystemVerilog, C, and Assembly.
• Architect reusable UVM verification environments and utilize them for coverage-driven verification.
• Coordinate simulation, emulation, and formal verification efforts for various DUTs.
• Analyse coverage reports and assist in closing coverage gaps.
• Own verification quality metrics and closure plans.
• Automate regression and verification flows using scripting languages such as Python, Perl, or Shell.
• Collaborate with senior engineers and architects to ensure design quality and performance.
• Lead small teams and project-wide verification initiatives.
• Influence verification methodologies across projects.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

What you'll need

• Bachelor's or master's degree in Electronics/Electrical/Computer Engineering.
• 8-12 years of experience in design verification, preferably in CPU or CPU-based SoC verification.
• Hands-on experience with SystemVerilog, UVM, and constrained random verification.
• Familiarity with CPU architectures such as RISC-V, ARM, or MIPS.
• Basic understanding of cache and coherency concepts.
• Strong scripting skills in Python, Perl, or Shell.

Nice to have

• Deep expertise in UVM, assertions, coverage, and processor architecture.
• Exposure to RISC-V architecture, hands-on verification of any of the CPU architectures.
• Knowledge of interconnect protocols like AXI, AHB, ACE, or CHI protocols.
• Experience with FPGA prototyping or emulation platforms.