Technical Staff Engineer-Verification

Overview

Technical Staff Engineer focused on verification for communication semiconductor devices and subsystems within the Communications Business Unit Product Development team. The role provides technical leadership across verification planning, testbench architecture, coverage closure and sign-off readiness at block and top level.

What you'll do

• Own or contribute to verification architecture for leading-edge communications devices.
• Build system-level understanding of device applications and use it to define complete, risk-based verification plans.
• Collaborate with Product Marketing, Applications Engineers, System Architects, Designers and Customers to identify, record, track and verify device requirements.
• Partition verification scope across block, subsystem and device levels, including reusable verification components and coverage models.
• Participate in concept and feasibility studies for next-generation products by identifying verification risks, methodology needs and validation alignment early in the development cycle.
• Lead delivery of verified digital integrated circuits at the device, subsystem or block level as a Verification Architect, Verification Lead or Technical Leader.
• Mentor and provide technical direction to a small team of Verification Engineers.
• Partner with Design Leads and Architects to align implementation intent, verification strategy and sign-off expectations.
• Translate industry standards, market requirements and functional specifications into executable verification plans, coverage goals and measurable closure criteria.
• Develop verification platforms guided by UVM methodology and implemented with SystemVerilog, assertions and reusable verification components.
• Drive verification execution, debug, regression quality, coverage closure and sign-off readiness using industry-leading tools and flows.
• Develop or enhance technical expertise in technologies, verification methodologies, flows or standards.
• Contribute to verification best practices for industry standards such as Ethernet, OTN and related networking technologies.
• Provide subject-matter guidance to development teams within CBU on verification strategy, methodology, debug and closure.
• Enhance internal, proprietary verification flows and practices to improve efficiency, completeness, reuse and sign-off quality.
• Collaborate with Software, Validation, Applications, Production Engineering and Design teams to deliver production-worthy devices supported by robust verification evidence.

What you'll need

• Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering.
• 12+ years related experience.
• Excellent analytical and debugging skills and the ability to proactively solve issues.
• Proven ability to thrive on, learn and adapt to new methodologies and technologies.
• Strong coding skills.
• Experience using one or more of SystemVerilog/Verilog/VHDL, Tcl/Perl/Python, C/C++, XML.
• Demonstrated experience verifying complex digital integrated circuits using SystemVerilog, UVM, assertions, constrained-random testing, coverage-driven verification, formal verification or related methodologies.
• Excellent verbal and written communication skills in English.

Nice to have

• Familiarity with communication protocols such as Ethernet, ASA and others.
• Experience with Synopsys, Cadence or similar verification, simulation, formal, debug, coverage or regression management tool flows.
• Experience with state-of-the-art silicon process technologies and complex SoC verification environments.

Details

• Location: Bangalore, India.
• Travel time: 0% - 25%.