RISCV Infra System IP DV - Sr Lead Engineer

Overview

Sr Lead Engineer for RISC-V/IP system design verification in Qualcomm’s hardware engineering organization.

What you'll do

• Develop IP/Sub-system design verification test plans and test cases.
• Build and use UVM/SystemVerilog DV test bench components like checkers, trackers, scoreboards, assertions, and coverage.
• Drive functional coverage closure by following up with stakeholders on code coverage.
• Work with system architects and design/emulation teams to debug failures and close code/functional coverage.
• Debug regression signatures and identify bug fixes.
• Support post-silicon bring-up and HW-SW debug (plus).

What you'll need

• Have a BS/MS/PhD in CS or Electrical/Electronics/related fields.
• Have 3+ years (BS) or 2+ years (MS) or 1+ year (PhD) of hardware engineering or related work.
• Expertise in UVM and SystemVerilog DV test bench and associated collaterals.
• Knowledge of bus protocols including CHI/AHB/AXI/ACE/ACE-Lite and interconnect concepts.
• Understanding of ARM/RISC-V system architecture topics including virtual memory and power management fundamentals.
• Ability to communicate and collaborate with a large worldwide design organization.