Senior Engineer, CAD Physical Verification

Overview

Senior CAD Engineer responsible for improving EDA tools and physical layout, verification, and design flows for CMOS integrated circuits. The role focuses on production support, memory layout automation, and AI-enabled methodologies.

What you'll do

• Support memory layout teams by solving daily challenges and developing complete solutions.
• Identify flow improvement opportunities and develop automation solutions.
• Lead layout flow implementation using AI-assisted and automated workflows.
• Evaluate and implement tools to improve layout development flows.
• Develop methodologies for reliable layouts and faster time to market.
• Mentor junior team members.
• Develop AI-enabled approaches for semi-automated floorplanning and parasitic estimation.

What you'll need

• 5+ years of experience in layout automation, physical verification, or related domains.
• Experience customizing design environments and automation utilities for memory layout productivity.
• Experience with custom-memory place-and-route flows and tools such as Cadence Virtuoso or Synopsys Custom Compiler.
• Knowledge of physical verification issues including DRC, ERC, LVS, DFM, and antenna rule decks.
• Understanding of CMOS manufacturing, layout rules, EMIR, RC extraction, ESD, and latch-up.
• Programming fundamentals with exposure to Skill, Perl, Python, or Tcl.
• Linux working knowledge and a bachelor's or master's degree in Electronics, Electrical, or Computer Engineering.

Nice to have

• Experience with PDN analysis tools such as Totem or VoltusXFA/XA.
• Experience debugging Calibre or ICV physical verification rule deck issues.

Details

• Location: Hyderabad, India.