IP Logic Design Engineer

Overview

Lead FPGA RTL design and platform enablement for Altera development kits, spanning architecture, implementation, timing closure, board bring-up, interface validation, and system-level debug.

What you'll do

• Define FPGA architecture, microarchitecture, interfaces, registers, clocking, resets, and implementation plans.
• Design and maintain synthesizable Verilog and SystemVerilog RTL.
• Translate board and system requirements into RTL features, diagnostics, loopbacks, and test functions.
• Run Quartus Prime flows through synthesis, fitting, timing analysis, configuration, and release readiness.
• Bring up boards and validate clocks, resets, memory, interfaces, and production readiness.
• Validate interfaces through loopback, protocol, stress, interoperability, and corner-case testing.
• Lead reviews, mentor engineers, and drive cross-functional issues to root cause.

What you'll need

• 10+ years of professional FPGA RTL design, FPGA implementation, and board bring-up experience.
• Bachelor's or master's degree in Electrical, Electronics, Computer Engineering, or a related discipline.
• Strong Verilog and SystemVerilog synthesizable RTL skills.
• Hands-on Quartus Prime or equivalent FPGA-flow experience, including timing constraints and closure.
• Strong knowledge of digital design, clock-domain crossing, reset-domain crossing, and multi-clock systems.
• Experience with FPGA board bring-up, simulation, lint, CDC analysis, formal checks, and assertions.
• Experience with interfaces or IP including PCIe, Ethernet, DDR, transceivers, Avalon, AXI, or DMA.

Nice to have

• Python and Tcl automation experience in Linux environments.
• Experience with Signal Tap, JTAG, oscilloscopes, logic analyzers, and protocol analyzers.
• Experience reading schematics and collaborating with board, firmware, IP, and validation teams.

Details

• Location: Bengaluru, Karnataka, India
• Employment type: Regular
• Shift: Shift 1 (India)